mix helps shrink circuits
Ted Smalley Bowen,
Technology Research News
As manufacturers make ever smaller computer
chips in a continuing quest to speed the signals pulsing through integrated
circuits, components like the capacitors that store electric charge will
require a certain amount of finessing in order to function in smaller
One challenge in reducing the size of capacitors on chips is to lose as
little storage capacity as possible, since capacitance -- the ability
to retain a charge of electric current for a certain amount of time --
depends partly on surface area.
Chip makers have addressed this in a number of ways: etching deep trenches
in the silicon, stacking capacitors vertically, roughening the silicon
surface, and using highly insulating materials between the capacitor electrodes.
A group of researchers at the University of Massachusetts and IBM have
harnessed the self-assembly abilities of commonly-used polymers to create
tiny masks that allow them to etch smaller silicon capacitors than current
production methods permit.
The promise of the method is that it can be implemented with existing
chip-making equipment, allowing for a leap in miniaturization without
requiring a retooling of the production line, said Chuck T. Black, a researcher
at IBM’s T.J. Watson Research Center. “Our process is compatible with
all the tools used for production of microelectronic circuits," he said.
To form the masks, the researchers used thin films of diblock copolymers,
which are carbon-based chains of molecules made from chains of polystyrene
and polymethylmethacrylate molecules. Polystyrene is used to make many
hard plastics and styrofoam. Polymethylmethacrylate is used to make plexiglass.
The researchers coaxed the copolymers to self-assemble into a closely-spaced
hexagonal array of polymethylmethacrylate cylinders within a polystyrene
matrix by spincasting thin films of the diblock copolymer onto a silicon
wafer, then heating the wafer to 160 °C. Spincasting is the process of
spreading a thin, even coat of a liquid onto a surface by spinning the
The cylinders were roughly 12 nanometers in diameter and spaced about
thirteen nanometers apart, said Black. A nanometer is one millionth of
a millimeter. The diameter of the cylinders and the spacing between them
could be varied by altering the molecular weight of the polymer, he said.
The researchers then exposed the cylinders to ultraviolet light, which
broke down the polymethylmethacrylate and caused the polystyrene to form
cross-links, locking the structure together. They used acetic acid to
remove the polymethylmethacrylate, producing a porous template of polystyrene
useful in chip-making lithography.
The result was a template about 30 nanometers thick, with pits, or holes
measuring 30 nanometers across, said Black.
The template holes are about the size of a stack of six red blood cells.
The mask is close to an order of magnitude smaller than those produced
using today's commercial photolithography method, which can produce features
as small as about 200 nanometers, said Black. It's also considerably smaller
than the next generation of that method, which promises to produce features
as small as 150 nanometers, he said.
Polymethylmethacrylate can be processed using the same techniques as conventional
polymers used in chip making, and it's natural self-organizing properties
give it a size advantage over today's methods, said Black. “Because of
the self-organizing properties of this polymer resist, we can pattern
features at resolutions higher than any photolithographic technique,"
without using complicated tools.
The diblock copolymer masking method allowed the researchers to make a
capacitor with a large surface area and at the same time squeeze it onto
a small amount of chip surface simply because the template provided them
with such small and regular spaces.
The researchers used the masks and a beam of ions, or charged atoms, to
etch into the surface of a silicon wafer a three-dimensional capacitor
electrode that had 30 percent more capacitance than common planar, or
To make a metal oxide semiconductor (MOS) device like those used in computer
chips, they added an aluminum gate electrode to the capacitor.
Refinements are in order before the method is ready for commercial production,
said Thomas P. Russell, professor of polymer science and engineering and
director of the Materials Research Science and Engineering Center at the
University of Massachusetts at Amherst. These include figuring out a way
to address, or connect components made this way, he said.
The work is a novel approach to increasing capacitance per unit area,
said Vivek Subramanian, assistant professor of electrical engineering
and computer science at the University of California, Berkeley. “This
is very important for the DRAM [memory chip] industry in particular. Specifically,
the authors achieve pits that are 30 nanometers across, which is very
The work is applicable to the creation of other micro-devices, Subramanian
said. “The technique could be used to form pits for molecular landing
pads for biochips. I think this technique will be very useful in these
alternative fields,” he said.
To use the methods in making silicon-based integrated circuits, however,
the researchers will need to more finely control the size and spacing
of the template holes, he said.
The technique would also be more useful if it could be used in a stacked
cell, where capacitors are built not on the silicon wafer substrate itself,
but on overlaying polysilicon. “Since the technology will likely be used
in a stacked cell... the technique must be applied to polysilicon, which
will require some development work,” he said. But “neither of these problems
should be show stoppers, so I think this is a really important and useful
technique,” he added.
Black’s research colleagues at IBM were Kathryn W. Guarini, and Keith
R. Milkove. Russell’s colleagues at UMass were Shenda M. Baker and Mark
The researchers published their research in the July 16, 2001 issue of
the Applied Physics Letters. The work was funded by the National Science
Foundation (NSF), Department of Energy (DOE), and IBM.
Funding: Corporate, Government
TRN Categories: Semiconductors; Nanotechnology
Story Type: News
Related Elements: Technical paper, “Integration of Self-Assembled
Diblock Copolymers for Semiconductor Capacitor Fabrication,” Applied Physics
Letters, July 16, 2001. >
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