Chip architecture uses nanowires

By Eric Smalley, Technology Research News

One of the great promises of nanotechnology is the potential to assemble astronomical numbers of transistors and switches using fast, inexpensive chemical processes.

Researchers have made prototypes of such nanoelectronic fabrics, but there is a vast gulf between being able to make arrays of nanoscale transistors and finding ways to wire them together to make computer chips.

Researchers at Hewlett-Packard Laboratories are working out by computer simulation what can be built with nanoscale electronic components like the nanowire crossbar arrays previously developed by the company.

The researchers' simulation mapped standard computer circuits onto a nanowire crossbar architecture. The simulation showed that despite the high rate of defects in nanowire crossbar arrays, such architectures can be used to make computer processors by building in redundancy, and despite the need for a high degree of redundancy, nanowire crossbar arrays can contain as many as 100 times more devices in a given area than today's chip technologies.

Nanoelectronics could eventually replace today's silicon chipmaking techniques when today's techniques run their course in a decade or two.

Initial applications for nanoscale chip technologies are likely to be low-power chips like those used in sensors and other small wireless devices, and ultrasmall chips for controlling microscale and nanoscale machines, said Greg Snider, a consultant to HP Labs.

The researchers' nanoelectronics architecture uses three basic building blocks made from nanowire arrays: logic, buffer and routing tiles.

Logic tiles can be configured into simple arrangements of logic gates that carry out basic computation. Buffer tiles provide the electrically required separation between logic tiles. Routing tiles control the flow of signals between groups of logic tiles.

A mosaic of the tiles forms an electronic fabric that is a blank slate for laying out computer circuits.

Most of today's computer chips are made by etching entire complicated circuits into silicon wafers. Some chips are made from field programmable gate arrays (FPGAs), which allow circuits to be configured after the chip is manufactured. The researchers' architecture is a form of configurable hardware. In the nanowire architecture, circuits are configured by electronically activating specific nanowire junctions following blueprints created by circuit design software.

Nanowire arrays can be made simply and cheaply, but contain a large number of defects.

Ordinarily, even a few defects can ruin an entire chip in standard chipmaking processes. To eliminate defects, chipmaking facilities use the expensive combination of precision equipment and sterile environments.

In contrast, nanoelectronics architectures must be designed to allow for defects, said Snider. "Since we expect nanoelectronic fabrics to contain a great many defects, [we] address the problem and show through simulation how defects need not impact efficiency... at least up to a certain point," he said.

The researchers used the simulation to design a simple, 4-bit signal filtering microprocessor. They adjusted three variables: defect probability, maximum number of inputs per logic unit, and the percentage of crossbar elements available for configuring circuits. They made 50 attempts at configuring the microprocessor for each setting of the three variables. The success rate was over 90 percent for defect rates of up to six percent in general and over 90 percent for defect rates of up to 14 percent in one configuration, according to Snider.

The study had a number of limitations and assumptions, Snider said. It used only one microprocessor design, which might not be representative. The simulated defects were uniformly distributed, which avoided the complications of defect clusters. It was assumed that all defects can be found before configuring the chip. And the simulated defects were only junctions that were stuck open, or electrically inactive, rather than the more difficult to accommodate closed, or electrically active, position.

Many questions about building computer chips using nanoelectronics remain. "Performance is still an open issue," said Snider. "We are intentionally focusing on manufacturing techniques that have low cost," he said.

Though several research teams have made nanowire arrays and even prototype nanowire memory chips, there's a long way to go before practical devices are possible. "The biggest practical challenges are in physics, chemistry, fabrication," said Snider. "We are limited by what nature allows us to do."

The researchers are ultimately aiming to build whole computing systems at the nanoscale, said Snider. Practical applications of the nanowire crossbar architecture could take anywhere from 5 to 20 years to achieve, he said.

Snider's research colleagues were Philip Kuekes and R. Stanley Williams. The work appeared in the August 2004 issue of Nanotechnology. The research was funded by Hewlett-Packard Laboratories.

Timeline:   5-20 years
Funding:   Corporate
TRN Categories:  Nanotechnology; Integrated Circuits
Story Type:   News
Related Elements:  Technical paper, "CMOS-like Logic In Defective, Nanoscale Crossbars," Nanotechnology, August, 2004


September 8/15, 2004

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